Deploying DeepSeek-V4-Flash with a 1M Context Window Across Two DGX Sparks

Deploying large language models (LLMs) across distributed edge hardware presents a distinct set of engineering challenges—especially when pushing context windows to extreme boundaries such as 1,048,576 tokens (1M context). Hardware like the NVIDIA DGX Spark offers a unified CPU/GPU memory architecture with 128 GB of shared memory per node. While a single node is potent, enterprise workloads demanding massive active parameters and ultra-long contexts require interconnecting multiple nodes into a unified inference cluster.

In this tutorial, we will walk through the complete deployment setup of DeepSeek-V4-Flash (a 284B parameter MoE architecture with 13B active parameters) across two NVIDIA DGX Spark nodes linked over dual QSFP interconnects. We will address container runtime setups, custom CUDA kernels for GB10 compute architectures, multi-rail RoCE v2 network configuration, and critical memory isolation strategies required for unified memory architectures.

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Hardware Architecture and Network Interconnect Setup

Each NVIDIA DGX Spark host houses 128 GB of unified memory shared dynamically between the host operating system, CPU processes, and GPU execution contexts. Combining two nodes yields 256 GB of system memory, which is essential to fit the ~156 GB model weight payload of DeepSeek-V4-Flash alongside the massive KV cache footprint needed for 1M context evaluation.

       +-------------------------------------------------------+
       |                  Tailscale Mesh Network               |
       +---------------------------+---------------------------+
                                   |
            +----------------------v----------------------+
            |               Control Node / Mac            |
            |              (SSH Script Driver)            |
            +----------------------+----------------------+
                                   |
         +-------------------------+-------------------------+
         |                                                   |
+--------v-----------------------+                 +---------v----------------------+
| Node 1: DGX Spark (Head Node)  |                 | Node 2: DGX Spark (Worker Node)|
| 128 GB Unified Memory          |  Dual QSFP      | 128 GB Unified Memory          |
| PCIe GB10 Compute (12.1)       |  4x RoCE Link   | PCIe GB10 Compute (12.1)       |
| vLLM / Ray Head Container      |<===============>| vLLM / Ray Worker Container    |
+--------------------------------+                 +--------------------------------+

Uncovering the Dual QSFP Dual-Rail Topography

Connecting two DGX Sparks using two physical QSFP cables creates an unexpected networking topology. Because the underlying GB10 architecture routes each physical QSFP port across two discrete PCIe sub-connections, Linux exposes each physical link as two separate Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) devices.

When checking system interfaces, four distinct RoCE v2 devices appear per node:

# Physical Link 1 maps to:
rocep1s0f0
roceP2p1s0f0

# Physical Link 2 maps to:
rocep3s0f0
roceP4p1s0f0

To achieve high-throughput inter-node communications via NVIDIA Collective Communications Library (NCCL), all four interfaces must be explicitly configured. Failing to specify the exact interface map forces NCCL to fall back to standard TCP host sockets, reducing throughput from ~180 Gbit/s RDMA down to single-digit gigabit speeds.

Automated Network Verification Script (network.sh)

Before initiating the distributed container runtime, execute an automated verification script over SSH to inspect interface bindings, verify maximum transmission unit (MTU) sizes, and export the proper environment variables for NCCL.

#!/usr/bin/env bash
# network.sh - Verify multi-rail RoCE status across DGX Spark nodes

NODES=("spark-head